Last modified on October 27, 2016, 8:10 pm

CRTS 2016
 
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Keynote

Rodolfo Pellizzoni, "Timing Compositionality over Memory Hierarchies”

BIO: Rodolfo Pellizzoni is Associate Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He received his master degree from Scuola Superiore Sant'Anna in 2005 and his PhD from the University of Illinois at Urbana-Champaign in 2010. Rodolfo's main research interests are in real-time systems and timing analysis, with a particular focus on hardware/software architectures for timing predictability and safety certification.

ABSTRACT: Implementing safety-critical real-time systems on multicore platforms poses significant challenges. From an industrial perspective, a compositional design paradigm is highly desirable, where a software partition running on one core can be certified independently of the applications running on other cores. However, multicore systems typically comprise a large number of shared physical resources, such as caches, interconnections, DRAM channels, etc. Contention for access to such shared resources can significantly affect the performance of concurrent applications, making it difficult to independently verify software partitions.

In this talk, we first summarize and categorize the main sources of interference in the memory hierarchy of modern multicore systems, and we provide an overview of common isolation techniques discussed in the literature. We then show that due to the nature of COTS arbiters, existing compositional timing analyses can unfortunately be quite pessimistic. Therefore, we argue that there is a need to introduce new timing interfaces to model the joint usage of processor and memory/communication resources, and we discuss examples of how such interfaces might be constructed.

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