1998
OH slides History

OH slides

1999
SNART'99

The architecture we propose is a tight and loosely coupled MIMD architecture (Multiple Instruction Multiple Data). The SARA system will continue the line of systems, which have been developed at Västerås using distributed and global shared-memory. The scalability of these systems is generally restricted by the number of processors accessing shared memory or by the complexity of the interconnection network. We believe that these restrictions can be overcome by using new architectures. The traditional approach to attacking the memory system bottleneck has been to build deeper and more complex cache hierarchies and/or to distribute the functions to different local systems.

We also propose a mixed scheduling policy for the tasks.

The architecture is controlled by a centralized hardware unit (scheduler, communication and synchronization functions), and supported by a number of specialized hardware accelerators. The principle is to implement much of the software administration (today) in hardware and to use the technique of hardware parallelism to obtain better solutions. The software system will consist of a small software interface to the hardware, the other part being the application tasks that can be implemented in hardware or software.

The RTU and a small software interface are responsible for the handling of safety, for flexibility, application software, debugging etc. The implementation technique of the RTU is based on a paradigm involving the utilisation of hardware parallelism and it can therefore handle multiple simultaneously (real parallel). The RTU can administer a number of processors, tasks, cash information, different real-time scheduling algorithms etc. at the same time [Stärner96].

The new approach is defined by the following design objectives (goal):

1. Extreme Scaleable and Simpler, The architecture should be a scaleable open system with no theoretical limit [Dal94]. A node can consist of hundreds of processors and be structured in a hierarchy. The software can be structured as for one processor (including I/O, external interrupts etc.) and distributed dynamically or statically. ([Furunäs97] and [Stärner96]).
2. Flexibility for different software architectures - the opposite of today’s thinking, The architecture should be usable in a variety of user applications (hard and soft tasks, processors etc.) [Stancovic]. Different software architectures could use the same hardware architecture. Also performing changes of the program and hardware without stopping the process.
3. Observability and controllability, Easy debugging and performance monitoring. It should be possible to validate the behavioral and the time requirements of the real-time system in run time. Logging data and control flow for analyze and verification.
4. Efficiency and Performance, The system hardware should be based on state-of-the-art high performance commercial standard microprocessors, busses etc. and operating system accelerators. The performance of the system should be extremely scaleable and predictable, also the latency should be bounded in time.
5. Low Hardware and Software Overhead (simplifications), The non-productive software and hardware should be minimized [Lawson98].
6. Low-Cost/Real-time Performance Value, The architecture, components and implementation selected are to give low cost/real-time performance value. To achieve this FPGA and ASIC design is necessary.
7. Fault Tolerance, Many real-time applications are safety-critical, and they must function at least partially under severe disturbance conditions [Kopertz91]. Reliability and a high degree of availability are crucial in meeting today’s business needs.
8. Component oriented design, The software components should be memory protected and the qualities of the components should be visible.
9. Predictability, The software and hardware should be partly predictable. Some part could meet hard predictability requirements.

The research question is: will it be possible to meet the above objectives if software functions and new functions implements in hardware?

During the initial phases, the project will concentrate on a few of these objectives, that are both the most urgent, and that also serve as foundations for the others. Another of our ambitions is to build a test bench incorporating a real process, for example an industrial Robot. New cache algorithms, multiprocessor systems etc. are tested in a simple way today. We believe that such testing (to prove the correctness) should be performed in relation to a real process.

The project is based on a previous project sponsored by KK, industry and the university. The project has evaluated an accelerator (RTU) for single processor real-time operating systems and designed multiprocessor real-time systems [Lindh95]. The research project begin in 1989 at Erlangen (Germany) with one person engage and now it is 8 persons in the group. The group has worked during recent years with hardware design methodology and with successful industrial projects.

Mälardalens University began an MIMD architecture project in 1994 which to date has implemented about 10 different hardware accelerators for multiprocessor operating systems (two in ASICs) [Lindh95].

Figure 1: Architecture of RTU System [Lindh95]

The project has two main working groups:

1) Operating System and Hardware Architectures for Complex Real-Time Computer Systems is to concentrate on hardware architectures (including an operating system, RTU) for MIMD (Multiple Instruction multiple Data) multiprocessor computer systems. And also covering such aspects as extendibility, verification, validation, analysis, reliability, availability, safety, security, maintainability, real-time behavior models and functionality (problems with caching, pipeline etc.) and physical isolation of critical functions. The extendibility of a system is its capacity to accept the addition of further processors or other resources to the architecture without changing the real-time software. An important goal is to make the architectures simple and understandable, the number of gates being a secondary consideration. The challenges in this project are the development of new architectures, their verification and ease of analysis (understanding).

2) System on Chip, Design Methods and Tools for ASIC Design is to focus on a complex system (MCU; 6-9 million gates in three years). The design methodology is to take into account the physical effects of the architectural complexity of the geometry, the use of intellectual properties, methods (Hardware description language, synthesis, software/hardware verification, rapid prototyping etc.), concurrent engineering and productivity. Knowledge of the use of state of the art tools is an essential prerequisite. The major challenge is the development of the architecture for "system on chip" and verification methods.

Industrial case studies will be used to validate the results of the research.

The research method is based on three steps, the incremental refinement of specification, simulation and verification.

1. Specification is a state-of-art-work and a synthesis of all the knowledge of the group and the other groups. Design a computer model and/or a physical prototype.
2. Simulation of our prototype and review of the solutions in relation to the goals. Results articles.
3. Verification is a phase in which the results will be reviewed in a context close to reality.

Ten prototypes were designed for verification during the RTU project [Lindh95] and our experience with this model has been positive.

A major current problem is that most of our research validation is performed at laboratory scale which is of less interest to the industrial world. Despite our collaboration with industry in other respects, it has been difficult for us to obtain the time and support of industry necessary for us to perform validation in real industrial processes. We conclude that we must establish our own complex test bench installation to enable us to perform validation of our research results at an industrial scale. Our ambition remains to obtain the association of a real process with this test bench.

Allocation of responsibility for SARA 98,
- Architecture and task scheduling, Johan Stärner
- Architecture, communication and synchronization, Johan Furunäs
- Implementations aspects, IP system on chip, Joakim Adomat
- Software aspects, Mohamed El Shobaki
- Communication protocols, Anders Rosvall, Ashraf Fawzi
- Design methods with VHDL; Stefan Sjöholm