PROGRESS research projects

PG-CBD-CVer – Component Verification

Leader: Paul Pettersson Members: Paul Pettersson, Cristina Seceleanu, Jagadish Suryadevara, Aneta Vulgarakis Research group: Formal Modelling and Analysis of Embedded Systems Status: finished , start date: 2006-10-01 , End date: 2010-12-31 Funding: SSF (Progress), MDH

Overview The objective of this project is to develop techniques for the analysis of functional and non-functional properties of real-time embedded systems designs described in the Progress component model. The ultimate goal is to develop a tool that supports analysis by techniques based on model-checking of the Progress component model. Three activates needed to reach this goal: a formal semantics of the Progress component model; an analysis techniques based on model-checking tailored for component models with timing; and a tool for model-checking properties of the component model. In addition, the developed technique and tool will be applied in an industrial evaluation.

Latest project publications [ Show all publications ] A Resource-Aware Framework for Designing Predictable Component-Based Embedded Systems, Aneta Vulgarakis, Ph D Thesis, Mälardalen University, June, 2012 A Formal Analysis Framework for AADL, Stefan Björnander, Cristina Seceleanu, Kristina Lundqvist, Paul Pettersson, The Journal of Science and Technology, November, 2011 Verifying functional behaviors of automotive products in EAST-ADL2 using UPPAAL-PORT, Eun-Young Kang (former), Pierre Yves Schnobbens (external), Paul Pettersson, Proceedings of the 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP'11), Springer-Verlag, September, 2011