Staff

Jagadish Suryadevara, PhD student
E-mail:
Room:	U1-174
Phone:	021- 10 31 16
Research group:	Formal Modelling and Analysis of Embedded Systems
PhD supervisor:	Paul Pettersson
Web:	Official university homepage

Biography [ Show only research interests ]

Jagadish Suryadevara received B.Sc and M.Sc (Applied Mathematics) from Andhra University(Andhra Pradesh, India), and M.Tech (Computer Science) from Jawaharlal Nehru Technological University(AP,India). Previously he worked as Lecturer in 'Computer Science and Information Systems' group, Birla Institute of Technology and Science (BITS),India.

Jagadish Suryadevara has previously worked in the research area of UML specification of concurrent, reactive systems at Tata Institute of Fundamental Research (TIFR), India. His general research interests include UML, formal specification and verification, software architectures, and real-time systems.

Latest publications [ Show all publications ]

Analysis Support for TADL2 Timing Constraints on EAST-ADL Models, Arda Goknil (INRIA, France), Jagadish Suryadevara, Marie-Agnes Peraldi-Frati (Univ. of Nice & INRIA, Sophia-Antipolis), Frederic Mallet (Univ. of Nice & INRIA, Sophia-Antipolis), 7th European Conference on Software Architecture (ECSA), Montpellier, France, July, 2013

Timed Automata Modeling of CCSL Constraints, Jagadish Suryadevara, Ling Yin (East China Normal University, Shanghai, China), First International Workshop on Formal Techniques for Safety-Critical Systems, Kyoto, JAPAN, November, 2012

Design and Analysis Support for Abstract Models of Component-based Embedded Systems, Jagadish Suryadevara, Licentiate Thesis, Mälardalen University Press, June, 2011

Research projects

On-going:

Finished:

PG-CBD-CVer – Component Verification

Supervised BSc and MSc theses

Master Thesis - UML Profile for ProCOM component model

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Latest update: 2009.11.03