Staff

Jagadish Suryadevara, PhD student
E-mail:
Room:	U1-174
Phone:	021- 10 31 16
Research group:	Formal Modelling and Analysis of Embedded Systems
PhD supervisor:	Paul Pettersson
Web:	Official university homepage

Research interests [ Show full biography ]

Jagadish Suryadevara has previously worked in the research area of UML specification of concurrent, reactive systems at Tata Institute of Fundamental Research (TIFR), India. His general research interests include UML, formal specification and verification, software architectures, and real-time systems.

Latest publications [ Show all publications ]

Verifying MARTE/CCSL Mode Behaviors using UPPAAL, Jagadish Suryadevara, Cristina Seceleanu, Frederic Mallet (Univ. of Nice & INRIA, Sophia-Antipolis), Paul Pettersson, 11th International Conference on Software Engineering and Formal Methods (SEFM), Madrid, SPAIN, September, 2013

Validating EAST-ADL Timing Constraints using UPPAAL, Jagadish Suryadevara, 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), Spain, September, 2013

Analysis Support for TADL2 Timing Constraints on EAST-ADL Models, Arda Goknil (INRIA, France), Jagadish Suryadevara, Marie-Agnes Peraldi-Frati (Univ. of Nice & INRIA, Sophia-Antipolis), Frederic Mallet (Univ. of Nice & INRIA, Sophia-Antipolis), 7th European Conference on Software Architecture (ECSA), Montpellier, France, July, 2013

Research projects

On-going:

Finished:

PG-CBD-CVer – Component Verification

Supervised BSc and MSc theses

Master Thesis - UML Profile for ProCOM component model

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Latest update: 2009.11.03