2015 1st PhD Form Meeting

Order of the day: All presentations shall be informal and relaxed, with a view to facilitating interaction with the participants, to let them understand the topic of the research, and to appreciate its challenges and the value of the results being presented.

All presentations will be given a slot of 45 minutes in total, at least 15 of which to be devoted to interaction with the participants
4 May    
  Session 1: Timing Analysis Techniques  
09:00-09:45 Vincent Mussot (IRIT, Toulouse) Improving WCET Analysis Precision through Automata Product
09:45-10:30 Marco Ziccardi (Uni Padova) Measurement-Based Timing Analysis: the Probabilistic Approach
Break    
11:00-11:45 Gordana Rakic (Uni Novi Sad) SSQSA framework: Toward Worst-Case Execution Time Estimation
11:45-12:30 Mladen Skelin (NUST, Trondheim) Worst-case Performance Analysis of SDF-based Parametrized Dataflow Models
Lunch    
  Session 1 (continued): Timing Analysis Techniques  
14:00-14:45 Konstantin Berezovskyi (CISTER, Porto) Timing Analysis of General-Purpose Graphics Processing Units for Real-Time Systems
14:45-15:30 Rody Kersten (Uni Nijmegen) Software Analysis Methods for Resource-Sensitive Systems
Break    
  Session 2: Application Scheduling  
16:00-16:45 Davide Compagnin (Uni Padova) Experimental evaluation of optimal schedulers based on partitioned proportionate fairness
16:45-17:30 Jose Carlos Fonseca (CISTER, Porto) Scheduling techniques for real-time parallel applications
  Session 3 (avdanced): Multicore and Manycore Processors  
17:30-18:15 Rasmus Soerensen (DTU, Copenhagen) Multicore Message Passing with ARINC 653
Social Dinner (19:30-)    
     
5 May    
  Invited Talk  
09:00-09:45 Miroslav Popovic (Uni Novi Sad) Work-Span Analysis of Transactional Memory Programs
  Session 3 (continued): Multicore and Manycore Processors  
09:45-10:30 Javier Jalle (BSC, Barcellona) Improving Time Predictability of Multicores in Real-Time Systems: The Case of the Space Domain
Break    
11:00-11:45 Martin Frieb (Uni Augsburg) Research on a Reduced Complexity Many-Core Architecture
11:45-12:30 Milos Panic (BSC, Barcellona) Many-core Architectures for Critical Real-Time Embedded Systems
Lunch    
Departures