| Both the
properties of the software and the
hardware affect the execution time
of a program. Consequently, static
WCET analysis is usually divided
into three phases: a flow
analysis phase, deriving
information on the possible
execution paths through the
program, a low-level analysis
phase, which determines the timing
behaviour of instructions in the
program given the architectural
features of the target hardware,
and a final calculation
phase, where the costliest
execution path of the program
under analysis is found using
information from the first two
phases.
During the last couple of
years, our WCET analysis
research project has performed
research both within flow
analysis, low-level analysis and
calculation. The main result is
the flow analysis tool SWEET
(SWEdish Execution Time tool).
We have also developed a low
level analysis tool (low-sweet)
with support for V850 and ARM9.
We have successfully
investigated how to analyze the
timing effects of processor
pipelining. We have also
developed various calculation
methods, able to handle more
type of complex flow- and
hardware timing information than
traditional calculation schemes.
We have also performed a large
number of research-oriented WCET
case-studies towards
Swedish companies.
|
