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research groups



Formal Modelling and Analysis of Embedded Systems

Focus:Formal modeling, analysis, and verification of real-time and embedded systems
Leader: Paul Pettersson
Members: Paul Pettersson, Cristina Seceleanu, Jagadish Suryadevara, Stefan Björnander, Aida Causevic, Leo Hatvani, Raluca Marinescu
Former: Eun-Young Kang
Division:Division of Embedded Systems
Funding:SSF, VR, EU and MdH.
 

Ongoing research projects  [ Show all projects ]

 

Latest group publications   [ Show all group publications ]


Using Logic Coverage to Improve Testing Function Block Diagrams, Eduard Paul Enoiu, Daniel Sundmark, Paul Pettersson, International Conference on Testing Software and Systems, Elsevier, Istanbul, November, 2013

Verifying MARTE/CCSL Mode Behaviors using UPPAAL, Jagadish Suryadevara, Cristina Seceleanu, Frederic Mallet (Univ. of Nice & INRIA, Sophia-Antipolis), Paul Pettersson, 11th International Conference on Software Engineering and Formal Methods (SEFM), Madrid, SPAIN, September, 2013

Validating EAST-ADL Timing Constraints using UPPAAL, Jagadish Suryadevara, 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), Spain, September, 2013

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